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Low-Power Design Panel at GSA Technology Leadership Forum in Hsinchu. Dr. Chin-Chi Teng, ICD R&D Engineering Group Director, Cadence; Albert Li, Director Design Development Division, Global Unichip; C. J. Hsieh, VP, Faraday Technology Corporation; Susan Runowicz-Smith, Group Director Power Forward Initiative, Cadence; Nickey Lu, GSA; Dr. David Flynn, Fellow, ARM; Lung Chu, Corporate VP Cadence; YK Cheng, Deputy Director, Reference Design Flow Development Dept (RDFDD) Taiwan, TSMC.
Ron Wilson, Executive Editor of EDN magazine moderates Low-Power Design panel at FSA Technology Leadership Forum in Taipei. Panelists include Gagan Gupta, ARC International;
Chi-Ping Hsu, Cadence; L.C. Lu, TSMC; and C.J. Hseih, Faraday
Chi-Ping Hsu speaks at the India Semiconductor Association panel - December 2006
FSA's International collaboration series on low-power design hosted speakers Jan Willis from Cadence, Mike Clendenin from EETimes Asia, YC Wu, TSMC, Felix Fei, ARM, Nianfeng Li, Verisilicon, and Frank Childers, Si2. The event was held at Semicon - Shanghai in March 2007.
