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Power Forward Initiative Low-Power Design Summit


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Mark your calendars for the low-power design event of year. On October 1, 2008, the 33 member companies of the Power Forward Initiative (PFI) will host a free Low-Power Design Summit in San Jose, California.

During the jam-packed one-day agenda, PFI members will share their low-power design expertise—best practices and proven capabilities you can adopt to design energy-efficient wireless and wired electronics.

Interact with presenters/panelists in sessions focusing on design experiences, low-power IP, and architectural design topics
Participate in tabletop discussions and meet with experts during breaks
Hear from ecosystem suppliers about their advanced solutions that support a holistic low-power design methodology

What: One-day, technical Low-Power Design Summit hosted by the Power Forward Initiative. Enjoy a continental breakfast, lunch, and post-event cocktails/networking
When: October 1, 2008
Where: Cadence Design Systems, Pebble Beach Conference Room, Bldg. 5

Agenda
8:00am Registration and breakfast
9:00am Introduction
9:10am Keynote 1 – nPowering Change, Chris Malachowsky, NVIDIA
9:30am Track 1 – Low-power design in action
1. Power-gating on a high performance GPU; Jeffrey Yang, AMD
2. Low Power Design Considerations; David Lan, TSMC
3. ARM1176-JZFS CPU Based Low Power Subsystem; Methodology to Reduce Electrical and Functional Failure; Sachin Idgunji, ARM Inc.
4. Advanced low-power design; Tobing Soebroto, Cadence

Track 2 – Power optimized IP
1. Power-Efficient Sound Solutions from ARC; Akash Despande, ARC International
2. ARM Power Management Kit and iRM; Wolfgang Helfricht, ARM Inc.
3. CPF Flow for Highly-Configurable Interconnect IP; Scott Evans, Sonics, Inc.
4. Minimizing Design Complexity with Power Optimized Physical IP; Ken Brock, Virage Logic
11:40am Panel 1 – Deploying low power – what are the challenges?
Moderator: Susan Runowicz-Smith, Cadence
Panelists: Ameesh Desai, LSI; Anis Jarrar, Freescale Semiconductor; Herve Menager, NXP, Brani Buric, Virage Logic
12:40pm Lunch (tabletop exhibits)
1:30pm Track 3 – Low-power design applications
1. Ultra Low Power Implementation using CPF; Anis Jarrar, Freescale Semiconductor
2. Faraday: A Low Power Platform-based SoC; Albert Chen, Faraday Technology Corporation
3. Cadence 45nm Common Platform Reference Flow; Gary Cheung, Chartered Semiconductor
4. Pre-Design ASIC Power Estimates; Bob Eisenstadt, Alchip Technologies

Track 4 – Architectural low-power trade-off techniques
1. Architectural Trade-off Analysis; Thad McCracken, Chip Planning Solutions
2. Sequential Optimizations for Low Power; Anmol Mathur, Calypto
3. Early Power Analysis with CPF; Will Ruby, Sequence Design
4. Micro-architecture Power Tradeoffs at the Electronic System Level; Michael McNamara, Cadence Design Systems
3:40pm Keynote 2 – Carl Guardino, Silicon Valley Leadership Group
4:00pm Panel 2 – Enabling power-efficient design – how important is it to be green?
Moderator: Ron Wilson, EDN Executive Editor
Panelists: John Goodenough, ARM; Walter Ng, Chartered Semiconductor; Steve Carlson, Cadence; Carl Guardino, Silicon Valley Leadership Group, Ron Burns, Wipro
5:00pm Closing remarks
5:15pm Drinks/hors d’oeuvres (tabletop exhibits)

What you will hear

Experiences with successful deployment of advanced low-power techniques in real designs
Challenges faced and the solutions employed to address them
Ecosystem offerings from EDA, IP, foundry, IDM, ASIC, and design services suppliers that enable power-efficient design
Perspectives from project managers who have completed designs like the ones you may be currently working on

Who should attend

Anyone working on or considering an energy-efficient design project
Those seeking technical expertise, knowledge of ecosystem capabilities, and examples of production-proven low-power methodology in use today

About the PFI
Recognizing the urgent need for an automated, power-aware design infrastructure, industry leaders are collaborating through the Power Forward Initiative to drive the refinement and adoption of advanced Common Power Format-enabled low-power design methodologies. Members include Alchip, AMD, Applied Materials, ARC, ARM, Azuro, Cadence, Calypto, Denali, DNP, Faraday, Freescale, Fujitsu, Global Unichip, Globetech, Improv Systems, Mindtree, MIPS Technologies, NEC Electronics, NSW, NXP, Sequence, SMIC, Socle, Sonics, Tensilica, Toppan, TSMC, UMC, VeriSilicon, Virage Logic, Vivace, and Wipro.